A varactor is a variable capacitor, i.e., a capacitor whose capacitance can be changed as a function of one or more control signals. The term “varactor” is derived from “variable” and “reactor”, and means a device whose reactance can be varied in a controlled manner. The term “varicap”, derived from “variable” and “capacitor”, is also used to describe such a device.
Varactors are employed in various parts of electronic systems. For example, varactors are utilized in voltage-controlled oscillators (“VCOs”) of wireless communications systems. A VCO generates a local oscillator signal for use in performing heterodyne frequency conversion in transceiver circuitry of a wireless communication system. The frequency of the oscillator signal changes as a function of a control voltage. In a VCO, one or more varactors provide the variable capacitance of an inductive-capacitive combination that establishes the frequency of the oscillator signal.
FIG. 1 illustrates a conventional differential cross-coupled VCO connected between ground and a source of positive supply voltage VDD. The VCO in FIG. 1 consists of identical cross-coupled n-channel enhancement-mode insulated-gate field-effect transistors (“FETs”) QA and QB, identical fixed-value inductors LA and LB, current source IA, and identical varactors CA and CB. The VCO's oscillator signal, taken from the drain of FET QA or QB, is provided at variable oscillator frequency fO given as:
                              f          O                =                  1                      2            ⁢            π            ⁢                                                                                               L                    O                                    ⁢                                      C                    O                                                                                                          (        1        )            where LO is the fixed inductance of each of inductors LA and LB, and CO is the variable alternating-current (“AC”) capacitance of each of varactors CA and CB. A control voltage (not shown) is applied to varactors CA and CB to control the value of capacitance CO and thus oscillator frequency fO.
FIG. 2a depicts a conventional single-ended Colpitts VCO formed with n-channel enhancement-mode insulated-gate FET QC, fixed-value inductor LC, current source IC, fixed-value capacitor CC, and varactor CE. A differential version of the single-ended VCO of FIG. 2a is depicted in FIG. 2b. The VCO in FIG. 2b consists of identical common-gate n-channel insulated-gate FETs QC and QD, identical fixed-value inductors LC and LD, identical current sources IC and ID, identical fixed-value capacitors CC and CD, and varactor CF. Letting LO here represent the inductance of each of inductors LC and LD, the oscillator in each of FIGS. 2a and 2b provides an oscillator signal at variable frequency fO determined from Eq. 1 where capacitance CO is now the series combination of (a) the fixed capacitance of each of capacitors CC and CD and (b) either the variable capacitance of varactor CE or twice the variable capacitance of varactor CF. A control voltage (not shown) is applied to varactor CE or CF to control its AC capacitance and thus frequency fO.
Varactors such as varactors CA, CB, CE, and CF can be implemented in various ways. A common varactor is a semiconductor junction varactor formed with a p-n diode having a reverse-biased p-n junction. A simplified example of a conventional junction varactor is shown in FIG. 3 where item 20 is a p-type body region of a semiconductor body. Moderately doped (p) material of body region 20 forms p-n junction 22 with heavily doped n-type region 24. Regions 20 and 24 respectively constitute the diode's anode and cathode.
Cathode electrode 26 contacts cathode region 24 along the upper semiconductor surface. Body electrode 28 contacts body region 20, typically through heavily doped p-type material (not separately indicated). Although body electrode 28 is illustrated as contacting body region 20 along the lower semiconductor surface in FIG. 3, electrode 28 can contact region 20 at other locations, e.g., along the upper semiconductor surface.
Reverse bias voltage VR is applied between electrodes 26 and 28 to reverse bias p-n junction 22. Since cathode region 24 is of n-type conductivity, cathode electrode 26 is at a higher voltage than body electrode 28. Junction depletion region 30 extends along p-n junction 22. Because cathode region 24 is heavily doped relative to body region 20, the thickness of body-side portion 32 of depletion region 30 is much greater, e.g., 100 times greater, than the thickness of cathode-side portion 34. As reverse voltage VR increases, the thickness of depletion region 30 increases. Only the thickness increase of body-side portion 32 is, for simplicity, indicated in FIG. 3.
Let CVA generally represent the AC areal capacitance, i.e., the AC capacitance per unit area, of a varactor. Junction depletion region 30, largely body-side portion 32, in the junction varactor of FIG. 3 functions as the dielectric for a capacitor in which the adjoining non-depleted p-type material of body region 20 serves as one of the capacitor's plates while the adjoining non-depleted n-type material of cathode region 24 serves as the capacitor's other plate. Areal capacitance CVA of the junction varactor is the AC areal junction depletion capacitance CdJA given as:
                                                                        C                VA                            =                              C                dJA                                                                                        =                                                                    K                    SC                                    ⁢                                      ɛ                    0                                                                    t                  dJ                                                                                        (        2        )            where ε0 is the permittivity of free space, KSC is the permittivity constant of the semiconductor material (typically silicon), and tdJ is the average thickness of junction depletion region 30. Inasmuch as junction depletion thickness tdJ increases with increasing reverse voltage VR, varactor capacitance CVA varies as a function of voltage VR in the varactor of FIG. 3.
It is typically desirable that the ratio of the maximum value CVAmax of varactor capacitance CVA to the minimum value CVAmin of capacitance CVA be nigh. In cases where the p-type body material along p-n junction 22 is uniformly doped at concentration NB to at least the maximum achievable thickness of body-side depletion portion 32, junction depletion thickness tdJ is given approximately as:
                              t          dJ                =                                                                       2                ⁢                                  K                  SC                                ⁢                                                      ɛ                    0                                    ⁡                                      (                                                                  V                        R                                            +                                              V                        BI                                                              )                                                                              qN                B                                                                        (        3        )            where VBI is the built-in voltage of p-n junction 22, and q is the electronic charge. The maximum-to-minimum varactor capacitance ratio for uniform doping in depletion portion 32 of body region 20 is thereby limited approximately to:
                                          C                          VA              ⁢                                                          ⁢              max                                            C                          VA              ⁢                                                          ⁢              min                                      =                                                                                         V                                      R                    ⁢                                                                                  ⁢                    max                                                  +                                  V                  BI                                                                              V                                      R                    ⁢                                                                                  ⁢                    min                                                  +                                  V                  BI                                                                                        (        4        )            where VRmax and VRmin respectively are the maximum and minimum bias values of reverse voltage VR.
The varactor capacitance ratio can be increased to approximately the following value by doping the body material along p-n junction 22 in a non-uniform hyperabrupt manner so that the body dopant concentration decreases from a maximum value NBmax along the bottom of depletion region 30 at its minimum thickness to a minimum value NBmin along the bottom of region 30 at its maximum thickness:
                                          C                          VA              ⁢                                                          ⁢              max                                            C                          VA              ⁢                                                          ⁢              min                                      =                                                                       (                                                      N                                          B                      ⁢                                                                                          ⁢                      max                                                                            N                                          B                      ⁢                                                                                          ⁢                      min                                                                      )                            ⁢                              (                                                                            V                                              R                        ⁢                                                                                                  ⁢                        max                                                              +                                          V                      BI                                                                                                  V                                              R                        ⁢                                                                                                  ⁢                        min                                                              +                                          V                      BI                                                                      )                                                                        (        5        )            However, improving the capacitance ratio in this way necessitates an additional masked ion implantation into the varactor area and complicates the process for manufacturing an integrated circuit containing components other than the varactor.
Another type of semiconductor varactor is a depletion insulated-gate varactor often referred to as a depletion metal-oxide semiconductor (“MOS”) varactor. FIG. 4 illustrates a simplified example of a conventional depletion insulated-gate varactor created from a semiconductor body having p-type body region 40. Gate dielectric layer 42 extending along the upper semiconductor surface separates gate electrode 44 from moderately doped (p) material of body region 40. Body electrode 46, analogous to body electrode 28 in FIG. 3, contacts body region 40. Gate-to-body bias voltage VGB, which varies across a voltage range extending from some negative value to some positive value, is applied between electrodes 44 and 46.
With gate-to-body voltage VGB being positive so that gate electrode 44 is at a higher voltage than body electrode 46, surface depletion region 48 forms in body region 40 along the upper semiconductor surface below gate electrode 44. The structure then functions as a capacitor having two dielectrics situated in series between gate electrode 44 and the non-depleted p-type body material underlying surface depletion region 48. One of the dielectrics is gate dielectric layer 42 having AC areal capacitance CGDA given as:
                              C          GDA                =                                            K              GD                        ⁢                          ɛ              0                                            t            GD                                              (        6        )            where KGD is the permittivity constant of dielectric layer 42, and tGD is the average thickness of dielectric layer 42 along electrode 44. The other dielectric is surface depletion region 48 having AC areal capacitance CdsA given as:
                              C          dsA                =                                            K              SC                        ⁢                          ɛ              0                                            t            ds                                              (        7        )            where tds is the average thickness of surface depletion region 48. Areal capacitance CVA of the depletion insulated-gate varactor is the series combination of areal capacitances CGDA and CdsA. Accordingly, capacitance CVA is given as:
                              C          VA                =                              C            GDA                                1            +                                                                           (                                                            K                      GD                                                              K                      SC                                                        )                                ⁢                                                                         (                                                                  t                        ds                                                                    t                        GD                                                              )                                                                                                          (        8        )            where gate dielectric capacitance CGDA is determined from Eq. 6. Surface depletion thickness tds increases with increasing gate-to-body voltage VGB UP to the point at which voltage VGB reaches a threshold value VT0. Capacitance CVA thus decreases with increasing gate-to-body voltage VGB over the VGB range from zero to threshold value VT0.
Inversion layer 50 forms in body region 40 along the upper semiconductor surface below gate electrode 44 when gate-to-body voltage VGB reaches threshold value VT0. Further increase in voltage VGB causes the charge density in inversion layer 50 to increase. However, surface depletion thickness tds remains substantially fixed at maximum value tdsmax in high-frequency AC operation because inversion layer 50 provides the additional charge necessitated by the VGB increase. Hence, varactor capacitance CVA remains approximately constant as voltage VGB rises above VT0 in high-frequency operation. For low-frequency AC operation, recombination/regeneration effects actually cause capacitance CVA to rise toward gate dielectric capacitance CGDA as voltage VGB is progressively raised above VT0. In either case, capacitance CVA is at minimum value CVAmin when voltage VGB is approximately VT0.
FIG. 5 illustrates an example of how the ratio of varactor capacitance CVA to gate dielectric capacitance CGDA varies with gate-to-body bias voltage VGB for the depletion insulated-gate varactor of FIG. 4. Curve portions A and B in FIG. 5 respectively depict the high-frequency and low-frequency capacitance characteristics for the depletion varactor. Curve portion C represents the high-frequency capacitance characteristics for the deep depletion insulated-gate varactor of FIG. 6 discussed below.
When gate-to-body voltage VGB is negative in the depletion insulated-gate varactor of FIG. 4, majority carriers (holes) accumulate along the upper semiconductor surface below gate electrode 48. The thickness of surface depletion region 48 progressively decreases as voltage VGB is made progressively more negative, i.e., of progressively greater negative value. Varactor capacitance CVA becomes gate dielectric capacitance CGDA which is maximum varactor capacitance value CVAmax. The maximum-to-minimum varactor capacitance ratio for the depletion varactor is approximately:
                                          C                          VA              ⁢                                                          ⁢              max                                            C                          VA              ⁢                                                          ⁢              min                                      =                  1          +                                    t                              ds                ⁢                                                                  ⁢                max                                                    t              GD                                                          (        9        )            
The maximum-to-minimum capacitance ratio given by Eq. 9 for the depletion varactor is considerably higher than that typically achievable with a junction varactor because maximum depletion thickness tdsmax which determines minimum capacitance value CVAmin is typically several times gate dielectric thickness tGD which determines maximum capacitance value CVAmax. At state-of-the-art values for dielectric thickness tGD, the maximum-to-minimum capacitance ratio for a depletion insulated-gate varactor can readily be 10.
A deep depletion insulated-gate varactor, often termed a deep depletion MOS varactor, is an extension of a depletion insulated-gate varactor to include a p-n junction which enables the maximum-to-minimum varactor capacitance ratio to be increased further. A simplified example of a deep depletion insulated-gate varactor is presented in FIG. 6. Except as indicated below, the deep depletion varactor in FIG. 6 contains components 40, 42, 44, and 46 arranged the same as in the depletion varactor of FIG. 4. With variable gate-to-body bias voltage VGB applied between electrodes 44 and 46, the capacitance of the deep depletion varactor is taken between electrodes 44 and 46 as in the depletion varactor.
In addition to components 40, 42, 44, and 46, the deep depletion insulated-gate varactor includes one or two heavily doped n-type junction regions 52. Each n+junction region 52 forms a p-n junction 54 with body region 40 and is contacted by a junction electrode 56 along the upper semiconductor surface. Reverse bias voltage VR, a fixed electrical potential here, is applied between body electrode 46 and each junction electrode 56 to reverse bias corresponding p-n junction 54. Since each junction region 52 is of n-type conductivity, each junction electrode 56 is at a higher voltage than body electrode 46. A junction depletion region 58, which normally meets surface depletion region 48, extends along each p-n junction 54.
FIG. 6 illustrates the situation in which two junction regions 52 are present in a deep depletion insulated-gate varactor. With the two regions 52 being laterally separated from each other, the structure is similar to an insulated-gate FET except that regions 52 are electrically tied together rather than serving as source and drain. When only one region 52 is present, the other region 52 is typically replaced with dielectric material that laterally electrically isolates islands of the semiconductor material along the upper semiconductor surface.
The deep depletion insulated-gate varactor of FIG. 6 operates in basically the same way as the depletion insulated-gate varactor of FIG. 4 except that the presence of junction region(s) 52 causes inversion layer 50 to occur at a greater positive value of gate-to-body voltage VGB than in an otherwise corresponding depletion varactor. Maximum surface depletion thickness tdsmax in the deep depletion varactor is thus greater than in the corresponding depletion varactor. Referring to curve C of FIG. 5, capacitance ratio CVA/CGDA reaches a lower value with the deep depletion varactor than with the depletion varactor. Accordingly, minimum varactor capacitance value CVAmin reaches a lower value in the deep depletion varactor than in the depletion varactor. As a result, the deep depletion varactor achieves a higher maximum-to-minimum varactor capacitance ratio than the depletion varactor. In particular, the maximum-to-minimum capacitance ratio for a deep depletion varactor can readily be 15–20 at state-of-the-art values for gate dielectric thickness tGD.
Wong et al (“Wong”), “A Wide Tuning Range Gated Varactor,” IEEE J. Solid-State Circs., May 2000, pages 773–779, describes another type of semiconductor varactor. As generally shown in FIG. 7, Wong's varactor is created from n body region 60 of a semiconductor body. Using somewhat unusual terminology, Wong's varactor includes heavily doped p-type “source” 62 and heavily doped n-type “drain” 64 laterally separated from each other along the upper semiconductor surface. Gate dielectric layer 66 separates gate electrode 68 from moderately doped n-type body material situated between source 62 and drain 64. Wong reports that the varactor capacitance is defined as the capacitance looking into the drain node.
Wong's varactor is operated in two modes with source voltage VS being ground reference (0 volt) in both modes. In one mode, drain voltage VD is also at ground while gate voltage VG is variable. Surface depletion region 70 extends along the upper semiconductor surface below gate electrode 68 and meets drain 64. Surface depletion region 70 merges into junction depletion region 72 extending along the p-n junction between body region 60 and source 62. Reducing gate voltage VG in this mode causes the thickness of composite depletion region 70/72 to increase so that the varactor capacitance decreases. In the second mode, gate voltage VG is at ground while drain voltage VD is variable. Increasing drain voltage VD causes the thickness of junction depletion region 72 to increase, thereby reducing the varactor capacitance. Inversion along the upper semiconductor surface below gate electrode 68 limits the maximum thickness of junction depletion region 72 and thus the minimum varactor capacitance in this mode.
Wong reports maximum and minimum capacitance values which appear to yield a maximum-to-minimum varactor capacitance ratio of 3–4. This varactor capacitance ratio is relatively low and, in fact, is lower than that typically achievable with either of the depletion insulated-gate varactors described above. As in the other varactors described above, the maximum-to-minimum capacitance ratio in Wong is determined primarily by the device metallurgical structure and is largely not independently controllable by the circuit designer.
Switched-capacitor varactors are employed in some applications. Although a high maximum-to-minimum varactor capacitance ratio can be achieved with a switched-capacitor varactor, it typically occupies a large semiconductor layout area. Switched-capacitor varactors require switching control and thus are also relatively complex.
It would be desirable to have a varactor which is of relatively simple design and which can readily achieve a high maximum-to-minimum varactor capacitance ratio. It would also be desirable to be able to change the maximum-to-minimum varactor capacitance ratio by appropriately adjusting certain lateral varactor layout dimensions.